1. Field of the Invention
The present invention relates to a plasma processing apparatus of the capacitive coupling type, used for performing a plasma process on a target substrate in, e.g., a semiconductor processing system. The term “semiconductor process” used herein includes various kinds of processes which are performed to manufacture a semiconductor device or a structure having wiring layers, electrodes, and the like to be connected to a semiconductor device, on a target substrate, such as a semiconductor wafer or a glass substrate used for an LCD (Liquid Crystal Display) or FPD (Flat Panel Display), by forming semiconductor layers, insulating layers, and conductive layers in predetermined patterns on the target substrate.
2. Description of the Related Art
For example, in manufacturing semiconductor devices, plasma processes, such as etching, sputtering, and CVD (Chemical Vapor Deposition), are often used for processing a target substrate or semiconductor wafer. There are various plasma processing apparatuses for performing such plasma processes, but parallel-plate plasma processing apparatuses of the capacitive coupling type are the ones in mainstream use.
In general, a parallel-plate plasma etching apparatus of the capacitive coupling type includes a process chamber with a pair of parallel-plate electrodes (upper and lower electrodes) disposed therein. When a process is performed, while a process gas is supplied into the chamber, an RF (radio frequency) power is applied to one of the electrodes to form an RF electric field between the electrodes, thereby causing RF electric discharge. The process gas is turned into plasma by the RF electric field, thereby performing, e.g., plasma etching on a predetermined layer disposed on a semiconductor wafer.
For example, there is an apparatus of this kind in which an RF power is applied to the lower electrode on which the semiconductor wafer is placed. In this case, the lower electrode serves as a cathode electrode, and the upper electrode serves as an anode electrode. The RF power applied to the lower electrode is used for plasma generation and also for an RF bias applied to the target substrate.
In the parallel-plate plasma processing apparatus of the capacitive coupling type, the upper electrode serving as an anode electrode needs to be protected from metal contamination and wear-out. For this reason, the upper electrode is formed of a metal base body having a surface covered with a coating made of an oxide film or insulative ceramic with high resistance to plasma, such as Y2O3.
Plasma is generated by RF electric discharge caused between the electrodes, and electron and ion currents generated thereby are neutralized at the ground potential. Accordingly, relative to the ground potential, the insulating film covering the upper electrode comes to have a potential, by which the plasma potential is determined.
In recent years, design rules in manufacturing semiconductor devices have been increasingly miniaturized. Particularly, in plasma etching, it is required to improve the dimensional accuracy, selectivity relative to the mask and under-layer, and planar uniformity of the etching. For this reason, the recent trend is to use a lower pressure and lower ion energy in the process field within a chamber. This trend has brought about the use of an RF power with a frequency of 27 MHz or more, which is far higher than the frequency conventionally used.
However, where a lower pressure and lower ion energy are used, as described above, it becomes necessary to address a decrease in the planar uniformity of plasma potential, which previously had been negligible. Specifically, in conventional apparatuses using high ion energy, poor planar uniformity of plasma potential does not cause a serious problem. However, as the pressure and ion energy are set to be lower, poor planar uniformity of plasma potential can easily make the process less uniform and easily cause charge-up damage.
In this respect, U.S. Pat. No. 6,624,084 (Patent Document 1) discloses a technique concerning a plasma processing apparatus. Specifically, this document discloses a technique of improving the planar uniformity of self-bias on a wafer generated by RF bias application, to reduce micro defects, such as charge-up damage. In order to achieve this, current path reform means is disposed for that portion of the RF current path of the RF bias applied to the wafer that is close to the periphery of the wafer, to cause an RF current to flow toward the surface of the counter electrode facing the wafer. Alternatively, impedance adjusting means is used to cause the impedance from the RF bias to ground to be almost uniform planarly on the wafer.
However, the technique of Patent Document 1 requires the current path reform means or impedance adjusting means and thus makes the apparatus structure complicated. Further, this technique is not necessarily sufficient in the planar uniformity of plasma processing.